The processor memory unit is the interface between the processor and the caches. Currently, instruction caches are not simulated and are assumed to be perfect. RSIM also does not currently support virtual memory. A processor's accesses to its private data space (described in Section 5.1) are currently considered to be cache hits in all multiprocessor simulations and in uniprocessor simulations configured for this purpose. However, contention at all processor and cache resources and all memory ordering constraints are modeled for private accesses in all cases.

The most important responsibility of the processor memory unit is to insure that memory instructions occur in the correct order. There are three types of ordering constraints that must be upheld:

1. Constraints to guarantee precise exceptions
2. Constraints to satisfy uniprocessor data dependences
3. Constraints due to the multiprocessor memory consistency model

Constraints for precise exceptions

The RSIM memory system supports non-blocking loads and stores. To maintain precise exceptions, a store cannot issue before it is ready to be graduated; namely, it must be one of the instructions to graduate in the next cycle and all previous instructions must have completed successfully. A store can be allowed to graduate, as it does not need to maintain a space in the active list for any later dependences. However, if it is not able to issue to the cache before graduating, it must hold a slot in the memory unit until it is actually sent to the cache. The store can leave the memory unit as soon as it has issued, unless the multiprocessor memory constraints require the store to remain in the unit.

Loads always wait until completion before leaving the memory unit or graduating, as loads must write a destination register value. Prefetches can leave the memory unit as soon as they are issued to the cache, as these instructions have no destination register value. Furthermore, there are no additional constraints on the graduation of prefetches.

Constraints for uniprocessor data depedences

These constraints require that a processor's conflicting loads and stores (to the same address) appear to execute in program order. The precise exception constraint ensures that this condition holds for two stores and for a load followed by a store. For a store followed by a load, the processor may need to maintains this data dependence by enforcing additional constraints on the execution of the load. If the load has generated its address, the state of the store address determines whether or not the load can issue. Specifically, the prior store must be in one of the following three categories:

1. address is known, non-conflicting
2. address is known, conflicting
3. address is unknown

In the first case, there is no data dependence from the store to the load. As a result, the load can issue to the cache in all configuration options, as long as the multiprocessor ordering constraints allow the load to proceed.

In the second case, the processor knows that there is a data dependence from the store to the load. If the store matches the load address exactly, the load can forward its return value from the value of the store in the memory unit without ever having to issue to cache, if the multiprocessor ordering constraints allow this. If the load address and the store address only partially overlap, the load may have to stall until the store has completed at the caches; such a stall is called a partial overlap, and is discussed further in Chapter 11.

In the third case, however, the load may or may not have a data dependence on the previous store. The behavior of the RSIM memory unit in this situation depends on the configuration options. In the default RSIM configuration, the load is allowed to issue to the cache, if allowed by the multiprocessor ordering constraints. When the load data returns from the cache, the load will be allowed to complete unless there is still a prior store with an unknown or conflicting address. If a prior store is now known to have a conflicting address, the load must either attempt to reissue or forward a value from the store as appropriate. If a prior store still has an unknown address, the load remains in the memory unit, but clears the busy bit of its destination register, allowing further instructions to use the value of the load. However, if a prior store is later disambiguated and is found to conflict with a later completed load, the load is marked with a soft exception, which flushes the value of that load and all subsequent instructions. Soft-exception handling is discussed in Section 3.2.4.

There are two less aggressive variations provided on this default policy for handling the third case. The first scheme is similar to the default policy; however, the busy bit of the load is not cleared until all prior stores have completed. Thus, if a prior store is later found to have a conflicting address, the instruction must only be forced to reissue, rather than to take a soft exception. However, later instructions cannot use the value of the load until all prior stores have been disambiguated.

The second memory unit variation stalls the issue of the load altogether whenever a prior store has an unknown address.

Constraints for multiprocessor memory consistency model.

RSIM supports memory systems three types of multiprocessor memory consistency protocols:

• Relaxed memory ordering (RMO) [23] and release consistency (RC) [6]
• Sequential consistency (SC) [11]
• Processor consistency (PC) [6] and total store ordering (TSO) [26]

Each of these memory models is supported with a straightforward implementation and optimized implementations. We first describe the straightforward implementation and then the more optimized implementations for each of these models.

The relaxed memory ordering (RMO) model is based on the memory barrier (or fence) instructions, called MEMBARs, in the SPARC V9 ISA [23]. Multiprocessor ordering constraints are imposed only with respect to these fence instructions. A SPARC V9 MEMBAR can specify one or more of several ordering options. An example of a commonly used class of MEMBAR is a LoadStore MEMBAR, which orders all loads (by program order) before the MEMBAR with respect to all stores following the MEMBAR (by program order). Other common forms of MEMBAR instructions include StoreStore, LoadLoad, and combinations of the above formed by bitwise or (e.g. LoadLoad|LoadStore). Instructions that are ordered by the above MEMBAR instructions must appear to execute in program order. Additionally, RSIM supports the MemIssue class of MEMBAR, which forces all previous memory accesses to have been globally performed before any later instructions can be initiated; this precludes the use of the optimized consistency implementations described below.

Release consistency is implemented using RMO with LoadLoad|LoadStore fences after acquire operations and LoadStore|StoreStore fences before release operations.

In the sequential consistency (SC) memory model, all operations must appear to execute in strictly serial order. The straightforward implementation of SC enforces this constraint by actually serializing all memory instructions; i.e. a load or store is issued to the cache only after the previous memory instruction by program order is globally performed [19]. Further, stores in SC maintain their entries in the memory unit until they have globally performed to facilitate maintaining multiprocessor memory ordering dependences from stores to later instructions. Unless RSIM is invoked with the store buffering command line option (discussed in Chapter 4), stores in SC do not graduate until they have globally performed. Forwarding of values from stores to loads inside the memory unit is not allowed in the straightforward implementation of sequential consistency. MEMBARs are ignored in the sequential consistency model.

The processor consistency (PC) and total-store ordering (TSO) implementations are identical in RSIM. With these models, stores are handled just as in sequential consistency with store buffering. Loads are ordered with respect to other loads, but are not prevented from issuing, leaving the memory unit, or graduating if only stores are ahead of them in the memory unit. Processor consistency and total store ordering also do not impose any multiprocessor constraints on forwarding values from stores to loads inside the memory unit, or on loads issuing past stores that have not yet disambiguated. MEMBARs are ignored under the processor consistency and total store ordering models.

Beyond the above straightforward implementations, the processor memory unit in RSIM also supports optimized implementations of memory consistency constraints. These implementations use two techniques to improve the performance of consistency implementations: hardware-controlled non-binding prefetching from the active list and speculative load execution [5].

In the straightforward implementations of memory consistency models, a load or store is prevented from issuing into the memory system whenever it has an outstanding consistency constraint from a prior instruction that has not yet been completed at the memory system. Hardware-controlled non-binding prefetching from the active list allows loads or stores in the active list that are blocked for consistency constraints to be prefetched into the processor's cache. As a result, the access is likely to expose less latency when it is issued to the caches after its consistency constraints have been met. This technique also allows exclusive prefetching of stores that have not yet reached the head of the active list (and which are thus prevented from issuing by the precise exception constraints).

Speculative load execution allows the processor not only to prefetch the cache lines for loads blocked for consistency constraints into the cache, but also to use the values in these prefetched lines. Values used in this fashion are correct as long as they are not overwritten by another processor before the load instruction completes its consistency constraints. The processor detects potential violations by monitoring coherence actions due to sharing or replacement at the cache. As in the MIPS R10000, a soft exception is marked on any speculative load for which such a coherence action occurs [28]; this soft exception will force the load to reissue and will flush subsequent instructions. The soft exception mechanism used on violations is the same as the mechanism used in the case of aggressive speculation of loads beyond stores with unknown addresses. Speculative load execution can be used in conjunction with hardware-controlled non-binding prefetching.

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TOKYO, Japan (AP) -- Masaya Igarashi wants $200 headphones for his new iPod Touch, and he's torn between Nintendo's Wii and Sony's PlayStation 3 game consoles. When he has saved up again, he plans to splurge on a digital camera or flat-screen TV.

There's one conspicuous omission from the college student's shopping list: a new computer.

The PC's role in Japanese homes is diminishing, as its once-awesome monopoly on processing power is encroached by gadgets such as smart phones that act like pocket-size computers, advanced Internet-connected game consoles, and digital video recorders with terabytes of memory.

"A new PC just isn't high on my priority list right now," said Igarashi, who was shopping at a Bic Camera electronics shop in central Tokyo, and said his three-year-old desktop was "good for now."

"For the cost, I'd rather buy something else," he said.

Japan's PC market is already shrinking, leading analysts to wonder whether Japan will become the first major market to see a decline in personal computer use some 25 years after it revolutionized household electronics -- and whether this could be the picture of things to come in other countries.

"The household PC market is losing momentum to other electronics like flat-panel TVs and mobile phones," said Masahiro Katayama, research group head at market survey firm IDC.

Overall PC shipments in Japan have fallen for five consecutive quarters, the first ever drawn-out decline in PC sales in a key market, according to IDC. The trend shows no signs of letting up: In the second quarter of 2007, desktops fell 4.8 percent and laptops 3.1 percent.

NEC's and Sony's sales have been falling since 2006 in Japan. Hitachi said October 22 it will pull out of the household-computer business entirely in an effort to refocus its sprawling operations.

"Consumers aren't impressed anymore with bigger hard drives or faster processors. That's not as exciting as a bigger TV," Katayama said. "And in Japan, kids now grow up using mobile phones, not PCs. The future of PCs isn't bright."

PC makers beg to differ, and they're aggressively marketing their products in the countries where they're seeing the most sales growth -- places where residents have never had a PC. The industry is responding in two other ways: reminding detractors that computers are still essential in linking the digital universe and releasing several laptops priced below $300 this holiday shopping season.

And, though sales in the U.S. are slowing too, booming demand in the industrializing world is expected to buoy worldwide PC shipments 11 percent to an all-time high of 286 million in 2007. And, outside Japan, Asia is a key growth area, with second-quarter sales jumping 21.9 percent this year.

Hitachi had already stopped making PCs for individual consumers since releasing this year's summer models, although the Tokyo-based manufacturer will keep making some computers for corporate clients. Personal computers already accounted for less than 1 percent of Hitachi's annual sales.

It's clear why consumers are shunning PCs.

Millions download music directly to their mobiles, and many more use their handsets for online shopping and to play games. Digital cameras connect directly to printers and high-definition TVs for viewing photos, bypassing PCs altogether. Movies now download straight to TVs.

More than 50 percent of Japanese send e-mail and browse the Internet from their mobile phones, according to a 2006 survey by the Ministry of Internal Affairs. The same survey found that 30 percent of people with e-mail on their phones used PC-based e-mail less, including 4 percent who said they had stopped sending e-mails from PCs completely.

The fastest-growing social-networking site here, Mobagay Town, is designed exclusively for cell phones. Other networking sites such as mixi, Facebook and MySpace can all be accessed and updated from handsets, as can the video-sharing site YouTube.

And while a lot of the decline is in household PCs, businesses are also waiting longer to replace their computers, partly because recent advances in PC technology are only incremental, analysts say.

At a consumer electronics event in Tokyo in October, the mostly unpopular stalls showcasing new PCs contrasted sharply with the crowded displays of flat-panel TVs.

"There's no denying PCs are losing their spunk in Japanese consumers' eyes," said Hiroyuki Ishii, a sales official at Japan's top PC maker, NEC Corp. "There seems to be less and less things only a PC can do," Ishii said. "The PC's value will fade unless the PC can offer some breakthrough functions."

The slide has made PC manufacturers desperate to maintain their presence in Japanese homes. Recent desktop PCs look more like audiovisual equipment -- or even colorful art objects -- than computers.

Sony's desktop computers have folded up to become clocks, and its latest version even hangs on the wall. Laptops in a new Sony line are adorned with illustrations from hip designers like ZAnPon. NEC is trying to make its PCs' cooling fans quieter -- to address a common complaint from customers, it says.

Still, sluggish sales weigh on manufacturers.

NEC's annual PC shipments in Japan shrank 6.2 percent to 2.72 million units in 2006, though overall earnings have been buoyed by mobile phone and networking solutions operations. The trend continued in the first quarter of fiscal 2007 then there was a 14 percent decline from a year earlier.

Sony's PC shipments for Japan shrank 10 percent in 2006 from a year earlier. But it isn't about to throw in the towel -- yet.

"We feel we've reached a new stage in PC development, where consumers are looking for user-friendly machines to complement other electronics," said Hiroko Nakamura, a Sony official in Tokyo.

Sony's latest PCs, for example, come with a powerful program that can take photos and video clips and automatically edit them into a slideshow set to music.

Even Cupertino, California-based Apple, whose computer sales and market share are surging in the U.S., has seen Macintosh unit sales in Japan slip 5 percent year-on-year in the first nine months of 2007.

There are other reasons Japan is the first market to see PCs shrink, some analysts say.

"We think of Japanese as workaholics, but many don't take work home," said Damian Thong, a technology analyst at Macquarie Bank in Japan. "Once they leave the office, they're often content with tapping e-mails or downloading music on their phones," he said.

As Hitachi's shuttering of its household PC business demonstrates, making PCs has become less attractive. IBM Corp. also left the PC business in 2005, selling its computer unit to China's Lenovo Group.

But NEC's Ishii is persisting.

A blog (a portmanteau of web log) is a website where entries are written in chronological order and commonly displayed in reverse chronological order. "Blog" can also be used as a verb, meaning to maintain or add content to a blog.

Many blogs provide commentary or news on a particular subject; others function as more personal online diaries. A typical blog combines text, images, and links to other blogs, web pages, and other media related to its topic. The ability for readers to leave comments in an interactive format is an important part of many blogs. Most blogs are primarily textual, although some focus on art (artlog), photographs (photoblog), sketchblog, videos (vlog), music (MP3 blog), audio (podcasting) and are part of a wider network of social media. Micro-blogging is another type of blogging which consists of blogs with very short posts.

As of September 2007, blog search engine Technorati was tracking more than 106 million blogs

ScienceDaily (Dec. 25, 2003) — As notebook computers become thinner and lighter, the ever-present bulky power adapters used for line current approach the weight of the laptops, but smaller and lighter adapters may be on the way, thanks to piezoelectric technology, according to a Penn State electrical engineer.

"Electromagnetic transformers are shrinking slightly, but there are theoretical limitations in reducing the general size," says Dr. Kenji Uchino, professor of electrical engineering. "A piezoelectric motor and transformer can be much smaller and lighter."

Transformers are needed to convert the 115-volt, 60-cycle power available from a standard U.S. wall receptacle to the 13 to 14 volts direct current used by laptops.

"Eventually we would like to make it the size of a pen, but that is far away," says Uchino. "When we can do that, the adapter will be a component of the laptop, not attached to the cord as a separate piece. Right now, we can reduce the adapters to one-fourth of their current size."

Uchino notes that while his group targets the laptop or notebook computer market, these smaller adapters are suitable for any appliance that requires an ac to dc converter and transformer.

Reporting in The Proceedings of the 5th International Conference on Intelligent Materials, Uchino, who heads the International Center for Actuators and Transducers at Penn State; T. Ezaki, Taiheiyo Cement Corporation, Japan; and A. Vazquez Carazo, Face Electronics, described their piezoelectric transformer.

Piezoelectric material moves when under an electric voltage, and, when displaced by outside pressure, these materials produce an electric voltage.

Transformers are made from piezoelectric materials by applying a chopped electric voltage to one side of a piezoelectric wafer. This on and off voltage creates a vibration in the material, which is converted to an ac voltage on the other side of the wafer. The amount of increase or decrease in the voltage transformed is dependent on the gap between the electrodes.

Most laptops require about 15 volts direct current with less than one amp of current and about 12 watts of power. By manipulating the length and width of the piezoelectric chip, the researchers can convert 115 volts to 15 volts. A rectifier then converts the alternating current to direct current.

The original piezoelectric devices were rectangular, but they could not produce sufficient power, so the researchers switched to a circular configuration.

"Smaller, less complex piezoelectric devices are already in use as step up transformers in some laptops to light the monitors which can take 700 volts to turn on and 50 to 150 volts to continue their operations," says Uchino.

One advantage of piezoelectric PC power adapters is that they do not produce the heat that conventional electromagnetic transformers produce. Electromagnetic power adapters not only produce heat, but also noise and interference. Piezoelectric power adapters operate in the ultrasonic range so humans cannot hear any sound produced and they do not produce electromagnetic interference.

"These power adapters were developed for the American and Japanese market where the line voltage is 100 to 125volts and 50 to 60 cycles," says Uchino. "Eventually, we also developed power adapters that convert 220 volts and 50 cycles so they can be used in the European market."

Other devices that could use these smaller, lighter power converters include printers, CD and DVD players, tape recorders and other appliances that operate on both battery and wall plugs.

The piezoelectric PC power adapter was developed at Penn State in collaboration with Face Electronics of Virginia and Taiheiyo Cement Corporation, Japan. Taiheiyo is planning to mass-produce the devices in 2004.

Adapted from materials provided by Penn State.


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ScienceDaily (Oct. 24, 2007) — Arizona State University's Center for Applied Nanoionics (CANi) has a new take on old memory, one that promises to boost the performance, capacity and battery life of consumer electronics from digital cameras to laptops. Best of all, it is cheap, made from common materials and compatible with just about anything currently on the market.

"In using readily available materials, we've provided a way for this memory to be made at essentially zero extra cost, because the materials you need are already used in the chips -- all you have to do is mix them in a slightly different way," said Michael Kozicki, director of CANi.

For some time now, conventional computer memory has been heading toward a crunch -- a physical limit of how much storage can be crammed into a given space. Traditional electronics begins to break down at the nanoscale -- the scale of individual molecules -- because pushing electronics closer together creates more heat and greater power dissipation. As consumer electronics such as MP3 players and digital cameras shrink, the need for more memory in a smaller space grows.

Researchers have been approaching the problem from two directions, either trying to leapfrog to the next generation of memory, or refining current memory. CANi took both approaches, amping up performance via special materials while also switching from charge-based storage to resistance-based storage.

"We've developed a new type of old memory, but really it is the perfect memory for what's going to be required in future generations," Kozicki said. "It's very low-energy. You can scale it down to the nanoscale. You can pack a lot of it into a small space."

CANi was also able to overcome the limitations of conventional electronics by using nanoionics, a technique for moving tiny bits of matter around on a chip. Instead moving electrons among charged particles, called ions, as in traditional electronics, nanoionics moves the ions themselves.

"We've actually been able to move something the size of a virus between electrodes to switch them from a high resistance to a low resistance, which is great for memory," Kozicki said.

Most memory today stores information as charge; in the binary language of computers, this means that an abundance of charge at a particular site on a chip translated as a "one," and a lack of charge is translated as a "zero." The problem with such memory is that the smaller its physical size, the less charge it can reliably store.

Resistance-based memory, on the other hand, does not suffer from this problem and can even store multiple bits on one site. Moreover, once the resistance is set, it does not change, even when the power is switched off.

CANi's previous high-performance resistance-change memory has been licensed to three companies, including Micron Technology and Qimonda, and has attracted the attention of Samsung, Sony and IBM. However, it used some materials, specifically silver and germanium sulfide, previously unused by industry and therefore required new processes to be developed.

The real advancement of CANi's newest memory is that researchers discovered a way to use materials already common in chip manufacturing. Although "doping" -- mixing silicon with small amounts of conductive materials such as boron, arsenic or phosphorus -- has been common practice for years, copper in silicon dioxide was largely unheard of. In fact, it was strictly avoided.

"People have actually gone to great lengths to keep the silicon oxide and the copper apart," Kozicki said. "But in our case, we are very interested in mixing the copper with the oxide -- basically, so that it would become mobile and move around in the material."

"Because it can move in there, we can make a sort of nanoscale switch," he added. "This very, very small switch can be used in memory applications, storing information via a range of resistance values."

Industry has already shown interest in the new memory and, if all goes well, consumers could see it on the market within a few years.

"What it means is we could replace all of the memory in all sorts of applications -- from laptops to iPods to cell phones to whatever -- with this one type of memory," Kozicki said. "Because it is so low energy, we can pack a lot of memory and not drain battery power; and it's not volatile -- you can switch everything off and retain information. What makes this significant is that we are using materials that are already in use in the semiconductor industry to create a component that's never been thought of before."

The research was conducted in collaboration with Research Center Jülich in Germany. It was published in the October 2007 issue of the journal IEEE Transactions on Electron Devices in the article "Bipolar and Unipolar Resistive Switching in Cu-doped SiO2." The team included Christina Schindler, on loan from Germany to CANi, Sarath Chandran Puthen Thermadam of CANi, Kozicki, and Rainer Waser of the Institute for Solid State Research and Center for Nanoelectronics Systems and Information Technology in Jülich.

Adapted from materials provided by Arizona State University.

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